FPGA routing and routability estimation via Boolean satisfiability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Using SAT for combinational equivalence checking
Proceedings of the conference on Design, automation and test in Europe
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A mapping algorithm for defect-tolerance of reconfigurable nano-architectures
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Nano, quantum and molecular computing: implications to high level design and validation
Nano, quantum and molecular computing: implications to high level design and validation
Topology aware mapping of logic functions onto nanowire-based crossbar architectures
Proceedings of the 43rd annual Design Automation Conference
Defect-tolerant adder circuits with nanoscale crossbars
IEEE Transactions on Nanotechnology
NanoV: nanowire-based VLSI design
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Defect-Aware Nanocrossbar Logic Mapping through Matrix Canonization Using Two-Dimensional Radix Sort
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Proceedings of the International Conference on Computer-Aided Design
Reliable logic mapping on Nano-PLA architectures
Proceedings of the great lakes symposium on VLSI
Defect-tolerant logic hardening for crossbar-based nanosystems
Proceedings of the Conference on Design, Automation and Test in Europe
ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Programmable logic arrays (PLAs) using self-assembly nanowire crossbars have shown promising potential for future nano-scale circuit design. However, due to the density and size factors of nanowires and molecular switches, the fabrication fault densities are much higher than those of the conventional silicon technology, and hence pose greater design challenges. In this paper, we propose a novel defect-aware logic mapping framework via Boolean satisfiability (SAT). Compared with the prior works, our technique considers PLA defects on both input and output planes at the same time. This synergistic approach can help solve logic mapping problems with higher defect rates. The proposed method is universally suitable for various nano-scale PLAs, including AND/OR, NOR/NOR structures, etc. The experimental results have shown that it can efficiently solve large mapping problems at a total defect rate of 20% or even higher. We further investigate the impact of different defects on PLA mapping, which helps set up an initial contribution for yield estimation and utilization of partially-defective PLAs.