Reliable logic mapping on Nano-PLA architectures

Authors:
Masoud Zamani;Mehdi B. Tahoori
Affiliations:
Northeastern University, Boston, MA, USA;Karlsruhe Institute of Technology, Karlsruhe, Germany
Venue:
Proceedings of the great lakes symposium on VLSI
Year:
2012

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Abstract

Programmable nano-architectures fabricated using bottom up self assembly are promising alternatives to CMOS circuits. However, extreme process variation and high defect rate are major challenges in this nanotechnology. In this paper, we present variation and defect aware logic mapping algorithms for these nano-architectures. Simulation results show that the proposed logic transformations and the mapping algorithms based on them can improve manufacturing yield by 65% with only 12.5% area overhead.