Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs
Proceedings of the conference on Design, automation and test in Europe
Variation tolerant logic mapping for crossbar array nano architectures
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Single-walled carbon nanotube electronics
IEEE Transactions on Nanotechnology
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Reliable logic mapping on Nano-PLA architectures
Proceedings of the great lakes symposium on VLSI
ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Programmable nano-architectures fabricated based on bottom-up self-assembly process are alternative for CMOS technology to overcome physical barriers as well as increased lithography-based fabrication costs in downscaling. Extreme process variation and high failure rate due to nondeter-ministic self assembly fabrication process pose serious challenges for logic implementation in this technology. In this paper, we analyze the effect of variations on mapped designs and propose an efficient mapping method to reduce variation effects on crossbar nano-architectures. This method takes advantage of reconfigurability and abundance of resources for tolerating variation and improving reliability. The main idea is based on duplicating crossbar input lines as well as swapping rows (columns) of a crossbar to reduce the output dependency and be able to reduce delay variation. Experimental results on a set of benchmarks show that the proposed method can reduce critical path delay up to 74% (57% in average).