Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Defect-tolerant nanoelectronic pattern classifiers: Research Articles
International Journal of Circuit Theory and Applications - Nanoelectronic Circuits
Spike-timing-dependent learning in memristive nanodevices
NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
IEEE Spectrum
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Robust learning approach for neuro-inspired nanoscale crossbar architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
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This work discusses the modeling of memristive devices, for architectures where they are used as synapses. It is shown that the most common models used in this context do not always accurately reflect the actual behavior of popular devices in pulse regime. We introduce a new behavioral model, intended towards the nanoarchitecture community. It fits the conductance evolution of Univ. Michigan's synaptic memristive devices. A variation of the model fits HP labs's memristors' behavior in the same conditions. Finally, we discuss using a simple example the importance of this type of modeling for learning architectures and how it can impact the behavior of the learning.