Compact floating-gate learning array with STDP
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
Fractional-order memristive systems
ETFA'09 Proceedings of the 14th IEEE international conference on Emerging technologies & factory automation
Evolving spiking networks with variable memristors
Proceedings of the 13th annual conference on Genetic and evolutionary computation
Evolving spiking networks with variable memristors
ACM SIGEVOlution
Emerging non-volatile memories: opportunities and challenges
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Robust neural logic block (NLB) based on memristor crossbar array
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Learning with memristive devices: How should we model their behavior?
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Memristive devices in computing system: Promises and challenges
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special issue on memory technologies
Memristor PUFs: a new generation of memory-based physically unclonable functions
Proceedings of the Conference on Design, Automation and Test in Europe
Evolving spiking networks with variable resistive memories
Evolutionary Computation
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The neuromorphic paradigm is attractive for nanoscale computation because of its massive parallelism, potential scalability, and inherent defect-, fault-, and failure-tolerance. We show how to implement timing-based learning laws, such as spike-timing-dependent plasticity (STDP), in simple, memristive nanodevices, such as those constructed from certain metal oxides. Such nano-scale “synapses” can be combined with CMOS “neurons” to create neuromorphic hardware several orders of magnitude denser than is possible in conventional CMOS. The key ideas are: (1) to factor out two synaptic state variables to pre- and post-synaptic neurons; and (2) to separate computational communication from learning by time-division multiplexing of pulse-width-modulated signals through synapses. This approach offers the advantages of: better control over power dissipation; fewer constraints on the design of memristive materials used for nanoscale synapses; learning dynamics can be dynamically turned on or off (e.g. by attentional priming mechanisms communicated extra-synaptically); greater control over the precise form and timing of the STDP equations; the ability to implement a variety of other learning laws besides STDP; better circuit diversity since the approach allows different learning laws to be implemented in different areas of a single chip using the same memristive material for all synapses.