FPGA Intrinsic PUFs and Their Use for IP Protection
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Overview of candidate device technologies for storage-class memory
IBM Journal of Research and Development
Spike-timing-dependent learning in memristive nanodevices
NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
Nonvolatile memristor memory: device characteristics and design implications
Proceedings of the 2009 International Conference on Computer-Aided Design
Memristor based programmable threshold logic array
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
A Formalization of the Security Features of Physical Functions
SP '11 Proceedings of the 2011 IEEE Symposium on Security and Privacy
DfT schemes for resistive open defects in RRAMs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
Memristors are emerging as a potential candidate for next-generation memory technologies, promising to deliver non-volatility at performance and density targets which were previously the domain of SRAM and DRAM. Silicon Physically Unclonable Functions (PUFs) have been introduced as a relatively new security primitive which exploit manufacturing variation resulting from the IC fabrication process to uniquely fingerprint a device instance or generate device-specific cryptographic key material. While silicon PUFs have been proposed which build on traditional memory structures, in particular SRAM, in this paper we present a memristor-based PUF which utilizes a weak-write mechanism to obtain cell behaviour which is influenced by process variation and hence usable as a PUF response. Using a model-based approach we evaluate memristor PUFs under random process variations and present results on the performance of this new PUF variant.