Analog VLSI: Circuits and Principles
Analog VLSI: Circuits and Principles
Neuromorphic architectures for nanoelectronic circuits: Research Articles
International Journal of Circuit Theory and Applications - Nanoelectric Circuits
Analog computing arrays
Low-Power Programmable Signal Processing, invited
IWSOC '05 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications
A Neuromorphic aVLSI network chip with configurable plastic synapses
HIS '07 Proceedings of the 7th International Conference on Hybrid Intelligent Systems
Spike-timing-dependent learning in memristive nanodevices
NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
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In this paper, we present a Spiking Neural Network (SNN) architecture that incorporates Integrate-and-fire (IF) type neurons and floating-gate transistors (FGTs) to store the synaptic weights. Compactness of the network has been the major target throughout the design. We believe that a CrossNet architecture lends itself very well to satisfy this goal. The synaptic weights are updated locally according to an approximation of Spike-Timing-Dependent Plasticity (STDP) rule. While the computations are performed internally in the analog domain the network is interfaced with a digital Address-Event-Representation (AER) to achieve robust off-chip communication. The operation of the array is described and selected simulations with 65nm CMOS are shown.