A Neuromorphic aVLSI network chip with configurable plastic synapses

Authors:
P. Camilleri;M. Giulioni;V. Dante;D. Badoni;G. Indiveri;B. Michaelis;J. Braun;P. del Giudice
Affiliations:
Otto-von-Guericke University, Magdeburg, Germany;Italian National Inst. of Health and INFN, Rome, Italy;Italian National Inst. of Health and INFN, Rome, Italy;INFN-RM2, Rome, Italy;ETHZ, Zurich, Switzerland;Otto-von-Guericke University, Magdeburg, Germany;Otto-von-Guericke University, Magdeburg, Germany;Italian National Inst. of Health and INFN, Rome, Italy
Venue:
HIS '07 Proceedings of the 7th International Conference on Hybrid Intelligent Systems
Year:
2007

Citing 0
Cited 5

Compact floating-gate learning array with STDP

IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
A systematic method for configuring vlsi networks of spiking neurons

Neural Computation
Hardware realization of BSB recall function using memristor crossbar arrays

Proceedings of the 49th Annual Design Automation Conference
2013 Special Issue: Computing with networks of spiking neurons on a biophysically motivated floating-gate based neuromorphic integrated circuit

Neural Networks
A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoring

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

We describe and demonstrate the key features of a neu- romorphic, analog VLSI chip (termed F-LANN) hosting 128 integrate-and-fire (IF) neurons with spike-frequency adap- tation, and 16 384 plastic bistable synapses implementing a self-regulated form of Hebbian, spike-driven, stochastic plasticity. We were successfully able to test and verify the basic operation of the chip as well as its main new fea- ture, namely the synaptic configurability. This configura- bility enables us to configure each individual synapse as either excitatory or inhibitory and to receive either recur- rent input from an on-chip neuron or AER (Address Event Representation)-based input from an off-chip neuron. It's also possible to set the initial state of each synapse as po- tentiated or depressed, and the state of each synapse can be read and stored on a computer. The main aim of this chip is to be able to efficiently perform associative learning ex- periments on a large number of synapses. In the future we would like to connect up multiple F-LANN chips together to be able to perform associative learning of natural stimulus sets.