Analog VLSI and neural systems
Analog VLSI and neural systems
Spike-timing-dependent learning in memristive nanodevices
NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
Robust learning approach for neuro-inspired nanoscale crossbar architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
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Neural networks are considered as promising candidates for implementing functions in memristor crossbar array with high tolerance to device defects and variations. Based on such arrays, Neural Logic Blocks (NLB) with learning capability can be built to replace Configurable Logic Block (CLB) in programmable logic circuits. In this article, we describe a neural learning method to implement Boolean functions in memristor NLB. By using Monte-Carlo simulation, we demonstrate its high robustness against most important device defects and variations, like static defects and memristor voltage threshold variability.