Low power architecture of the soft-output Viterbi algorithm
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Turbo code implementation issues for low latency, low power applications
Wireless personal communications
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
High Rate Soft Output Viterbi Decoder
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Iterative decoding of binary block and convolutional codes
IEEE Transactions on Information Theory
IEEE Journal on Selected Areas in Communications
Design of low-power high-speed maximum a priori decoder architectures
Proceedings of the conference on Design, automation and test in Europe
Energy efficient turbo decoding for 3G mobile
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Architectural strategies for low-power VLSI turbo decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory Power Reduction for High-Speed Implementation of Turbo Codes
Journal of VLSI Signal Processing Systems
A low-power VLSI architecture for turbo decoding
Proceedings of the 2003 international symposium on Low power electronics and design
VLSI architectures for SISO-APP decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Scalable System Architecture for High-Throughput Turbo-Decoders
Journal of VLSI Signal Processing Systems
Architecture-driven voltage scaling for high-throughput turbo-decoders
Journal of Embedded Computing - Low-power Embedded Systems
Area-efficient high-throughput MAP decoder architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |