High Rate Soft Output Viterbi Decoder

Authors:
Eric Luthi;Emmanuel Casseau
Affiliations:
Integrated Circuits for Telecommunications Laboratory, Ecole Nationale Supérieure des Télécomunications de Bretagne, BP 832-29285 Brest Cedex FRANCE;Integrated Circuits for Telecommunications Laboratory, Ecole Nationale Supérieure des Télécomunications de Bretagne, BP 832-29285 Brest Cedex FRANCE
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

Citing 1
Cited 1

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Abstract

This paper presents the architecture of a high rate soft output Viterbi decoder (100 Mb/s for worst case process conditions, 8 states, coding rate R=1/2, using a 0.6ym CMOS technology), using the "radix" trellis method (collapsed trellis) to speed up the rate of a soft output decoder using the Viterbi algorithm and the a posteriori weighting algorithm. The size of this circuit is roughly twice that of the original soft output Viterbi decoder while the speed is increased by a factor of 2. Because of its performances, this circuit is very attractive for satellite digital communication systems and is at the root of "turbo-codes", which are a new class of convolutional codes whose performances, in terms of bit error rate, are close to the Shannon limit.