Hardware/Software Trade-Offs for Advanced 3G Channel Coding

Authors:
H. Michel;A. Worm;N. Wehn;M. Münch
Affiliations:
University of Kaiserslautern, Institute of Microelectronic System Design, Erwin-Schroedinger-Strasse, 67663 Kaiserslautern, Germany;University of Kaiserslautern, Institute of Microelectronic System Design, Erwin-Schroedinger-Strasse, 67663 Kaiserslautern, Germany;University of Kaiserslautern, Institute of Microelectronic System Design, Erwin-Schroedinger-Strasse, 67663 Kaiserslautern, Germany;Alcatel, ASIC Design Labs, Excelsiorlaan 44-46, 1930 Zaventem, Belgium
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2002

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Abstract

Third generation's wireless communications systemscomprise advanced signal processing algorithms that in-creasethe computational requirements more than ten-foldover 2G's systems. Numerous existing and emerging standardsrequire flexible implementations ("software radio").Thus efficient implementations of the performance-criticalparts as Turbo decoding on programmable architecturesare of great interest. Besides high-performance DSPs,application-customized RISC cores offer the required performancewhile still maintaining the aspired flexibility. Thispaper presents for the first time Turbo decoder implementationson customized RISC cores and compares the resultswith implementations on state-of-the-art VLIW DSPs. Theresults of our studies show that the Log-MAP performanceis about 50 % higher than on an ST120, a current VLIWarchitecture.