A generic scalable architecture for min-sum/offset-min-sum unit for irregular/regular LDPC decoder

Authors:
Venkata K. Kidambi Srinivasan;Chitranjan K. Singh;Poras T. Balsara
Affiliations:
Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX;Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX;Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

Citing 6
Cited 1

Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding

ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
Disclosing the LDPC code decoder design space

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation

ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Good error-correcting codes based on very sparse matrices

IEEE Transactions on Information Theory
Factor graphs and the sum-product algorithm

IEEE Transactions on Information Theory
Design of capacity-approaching irregular low-density parity-check codes

IEEE Transactions on Information Theory

Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

The most common algorithm used in iterative decoding of low-density parity check (LDPC) codes is based on a generic class of the sum-product algorithm, which has a nonlinear dependence on the log(tanh()) function. The implementation based on fixed precision has substantial loss of accuracy and is computationally expensive with full precision. A suboptimal version of belief propagation called the offset-min-sum algorithm is generally used in hardware implementation. This paper proposes a generic scalable architecture for minimum search during check-node operation in the offset-min-sum algorithm applicable to regular as well as irregular LDPC codes with check node of any degree d. For an LDPC code with maximum check node degree d, the proposed architecture consists of 2(d - 2) 2 × 1 multiplexers and 3(d - 2) two-input compare-and-select units (CSUs). This has latency of [2 ⌈log2(d)⌉ - 2]tdc when ⌈log2(d)⌉ - log2(d) 2 (4/3) else [2 ⌈log2(d)⌉ - 3]tdc, with tdc representing the delay of a two-input CSU. The proposed architecture has been implemented for d = 20 using a TSMC 0.18-µm CMOS process.