A Synthesizable IP Core for DVB-S2 LDPC Code Decoding
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
The capacity of low-density parity-check codes under message-passing decoding
IEEE Transactions on Information Theory
Design of capacity-approaching irregular low-density parity-check codes
IEEE Transactions on Information Theory
Hardware that produces bounded rather than exact results
Proceedings of the 47th Design Automation Conference
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The Irregular Repeat Accumulate (IRA) codes introduced by Jin et al. [1] are structured Low Density Parity Check (LDPC) codes that are known to perform as well as the best unstructured LDPCs. IRAs reach rates that are quite close to capacity on the additive white Gaussian noise (AWGN) channel, can be both encoded and decoded in linear time, are perceived to be low complexity codes, and have been adopted into recent standards. Systematic with Serially Concatenated Parity (S-SCP) codes were recently introduced in [2], [3] as a class of turbo like codes with members that exhibit good performance over a wide range of block sizes, code rates, and target error probabilities. In this paper we introduce irregular designs for Systematic with Serially Concatenated Parity (Ir-S-SCP) codes and show that both for near-capacity and more practical lower-complexity designs, irregular two-state S-SCP codes can be designed to achieve the performance of IRA codes at lower complexity.