Performance evaluation and ASIC design of LDPC decoder for IEEE 802.11n

Authors:
W. A. Syafei;R. Yohena;H. Shimajiri;T. Yoshida;M. Kurosaki;Y. Nagao;B. Sai;H. Ochi
Affiliations:
Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan;Department of Information Engineering, University of the Ryukyus, Nishihara, Okinawa, Japan;Frontier Okinawa 21 Co., Ltd., Naha, Okinawa, Japan;Department of Information Engineering, University of the Ryukyus, Nishihara, Okinawa, Japan;Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan;Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan;Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan;Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka, Fukuoka, Japan and Radrix Co., Ltd., Japan
Venue:
CCNC'09 Proceedings of the 6th IEEE Conference on Consumer Communications and Networking Conference
Year:
2009

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Abstract

This paper presents our investigation on performance enhancement due to the implementation of low density parity check (LDPC) codes on IEEE 802.11n system and its Application Specific Integrated Circuit design. Simulation result shows that in higher coding rate, LDPC codes gives 6 dB better performance compared to binary convolutional codes. Logic synthesis is succesfully done on 0.13 µm CMOS technology with low-power standard cell library.