High-throughput decoder for low-density parity-check code

Authors:
Tatsuyuki Ishikawa;Kazunori Shimizu;Takeshi Ikenaga;Satoshi Goto
Affiliations:
Waseda University, Hibikino, Wakamatsuku, Kitakyushushi, Fukuoka, Japan;Waseda University, Hibikino, Wakamatsuku, Kitakyushushi, Fukuoka, Japan;Waseda University, Hibikino, Wakamatsuku, Kitakyushushi, Fukuoka, Japan;Waseda University, Hibikino, Wakamatsuku, Kitakyushushi, Fukuoka, Japan
Venue:
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Year:
2006

Citing 2
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Low-power VLSI decoder architectures for LDPC codes

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Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding

ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2

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Abstract

We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 530Mb/s at an operating frequency of 147MHz. The chip has been fabricated in a 0.18μm, 6 metal-layer CMOS technology. The chip size is 36mm2.