Parallel turbo-sum-product decoder architecture for quasi-cyclic LDPC codes

Authors:
Yongmei Dai;Zhiyuan Yan;Ning Chen
Affiliations:
Lehigh University, PA;Lehigh University, PA;Lehigh University, PA
Venue:
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Year:
2006

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Abstract

In this paper, we first propose a parallel turbo-sum-product (PTSP) decoding algorithm for quasi-cyclic (QC) low-density parity-check codes, and show that our proposed algorithm achieves better error performance and faster convergence than the sum-product (SP) or overlapped SP (OSP) algorithm. Based on our PTSP algorithm, we then propose a partly parallel decoder architecture, which requires smaller memory size, less memory access and power consumption, and simpler control than decoder architectures based on the OSP algorithm.