A dynamically reconfigurable adaptive viterbi decoder
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
A design flow for partially reconfigurable hardware
ACM Transactions on Embedded Computing Systems (TECS)
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This paper describes the design and implementation of Viterbi decoder using FPGAs.In this paper we explore an FPGA based implementation methodology for rapid prototyping designs. We use high level synthesis to achieve this.One of the main blocks of a CDMA modem used during forward-link demodulation is a Viterbi decoder. A normal Viterbi decoder for a constraint length of 9 (256 states) uses more than 15 kb of memory and can occupy as high as 1/3 of the modem chip area. Our aim was to design a 19.2 kbps, 256 state Viterbi decoder with the added capability of catering to higher input data rates. To the best of our knowledge none of the literature discusses Viterbi decoder implementation based on high level synthesis targeted for Field Programmable Gate Arrays (FPGAs). This has been the focus in the present paper.Besides the above, some of the issues such as organization of a path memory, decision memory, reading of the decision memory and the clocking mechanism have been discussed. We have also retained the bit-synchronization information, even though it made the normalization of the path metrics essential.