A dynamically reconfigurable adaptive viterbi decoder
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Power-Aware 3D Computer Graphics Rendering
Journal of VLSI Signal Processing Systems
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Signal processing algorithms and architectures can use dynamic reconfiguration to exploit variations in signal statistics with the objectives of improved performance and reduced power consumption. Parameters provide a simple and formal way to characterize incremental changes to a computation and its computing mechanism. This paper examines five parameterized computations which are typically implemented in hardware for a wireless multimedia terminal: (1) motion estimation, (2) discrete cosine transform, (3) Lempel-Ziv lossless compression, (4) 3D graphics light rendering and (5) Viterbi decoding. Each computation is examined for the capability of dynamically adapting the algorithm and architecture parameters to variations in their respective input signals. Dynamically reconfigurable low-power implementations of each computation are currently underway.