The program dependence graph and its use in optimization
ACM Transactions on Programming Languages and Systems (TOPLAS)
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Algorithms in C++
Instruction-level parallel processing
Instruction-level parallel processors
Advanced compiler design and implementation
Advanced compiler design and implementation
Speculation techniques for high level synthesis of control intensive designs
Proceedings of the 38th annual Design Automation Conference
IEEE MultiMedia
The Garp Architecture and C Compiler
Computer
Automatic Extraction of Functional Parallelism from Ordinary Programs
IEEE Transactions on Parallel and Distributed Systems
An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Parallelizing Applications into Silicon
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Cameron: High Level Language Compilation for Reconfigurable Systems
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
The Transmogrifier C hardware description language and compiler for FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Wavesched: a novel scheduling technique for control-flow intensive designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents new achievements on the automatic mapping of abstract algorithms, written in imperative software programming languages, to custom computing machines. The reconfigurable hardware element of the target architecture consists of one field-programmable gate array coupled with one or more memories. The compilation flow exposes operation- and functional-level parallelism, and speculative execution. Such expositions are efficiently represented in a hierarchical model. In order to take full advantage of such representation, the scheduling scope is significantly improved by merging basic blocks at loop boundaries and by considering the parallel execution of exposed concurrent loops. The paper describes the scheduling technique, shows a study on the impact of the merge operation, and reveals the improvements achieved when the exposed parallelism is fully satisfied.