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ACM Transactions on Programming Languages and Systems (TOPLAS)
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High-level synthesis: introduction to chip and system design
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Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
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FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
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FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
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FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Automatic generation of application-specific systems based on a micro-programmed Java core
Proceedings of the 2005 ACM symposium on Applied computing
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This paper presents new techniques for architecture and performance driven compilation of SW programs into RW (reconfigurable HW). These new techniques effectively improve on the complex resource sharing approaches typical of high-level synthesis algorithms, which are efficient for layout flexible ASICs but are clearly not adequate for reconfigurable devices with pre-defined architectures. The compilation flow takes advantage of a specialized library of circuit-generators and only resorts to logic synthesis for the generation of the data-path's control unit. The algorithms under development are being integrated onto an HW compiler that accepts programs previously compiled to Java™ Bytecodes. A series of experiments has been performed using a number of practical examples and the results achieved so far are very promising and indicate that the RW compilation techniques proposed can provide significant improvements over currently available methods.