Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Rapid Prototyping of a Co-Designed Java Virtual Machine
RSP '04 Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping
Fast hardware compilation of behaviors into an FPGA-based dynamic reconfigurable computing system
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture
Proceedings of the 2008 ACM symposium on Applied computing
A Java processor architecture for embedded real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
Using hardware methods to improve time-predictable performance in real-time Java systems
Proceedings of the 7th International Workshop on Java Technologies for Real-Time and Embedded Systems
Java bytecode to hardware made easy with bluespec system verilog
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
| Hi-index | 0.00 |
This paper describes a co-design based approach for automatic generation of application specific systems, suitable for FPGA-centric embedded applications. The approach augments a processor core with hardware accelerators extracted automatically from a high-level specification (Java) of the application, to obtain a custom system, optimised for the target application. We advocate herein the use of a microprogrammed core as the basis for system generation in order to hide the hardware access operations in the micro-code, while conserving the core data-path (and clock frequency). To prove the feasibility of our approach, we also present an implementation based on a modified version of the Java Optimized Processor soft core on a Xilinx Virtex-II FPGA.