System Design: A Practical Guide with Specc
System Design: A Practical Guide with Specc
The Verilog Hardware Description Language, 5th Edition
The Verilog Hardware Description Language, 5th Edition
Hardware Synthesis from Term Rewriting Systems
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
In-System FPGA Prototyping of an Itanium Microarchitecture
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Automatic generation of application-specific systems based on a micro-programmed Java core
Proceedings of the 2005 ACM symposium on Applied computing
BlueJEP: a flexible and high-performance Java embedded processor
JTRES '07 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems
BluEJAMM: A Bluespec Embedded Java Architecture with Memory Management
SYNASC '07 Proceedings of the Ninth International Symposium on Symbolic and Numeric Algorithms for Scientific Computing
Designing a concurrent hardware garbage collector for small embedded systems
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Investigating hardware micro-instruction folding in a Java embedded processor
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
High-level design and validation of the BlueSPARC multithreaded processor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
A monadic approach to automated reasoning for Bluespec SystemVerilog
Innovations in Systems and Software Engineering
Java bytecode to hardware made easy with bluespec system verilog
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
A Mersenne Twister Hardware Implementation for the Monte Carlo Localization Algorithm
Journal of Signal Processing Systems
Hi-index | 0.00 |
This paper compares two hardware design flows, based on the classic VHDL on one side and the relatively new Blue-spec System Verilog (BSV) on the other side. The comparison is based on a case study of a Java embedded architecture, comprising a Java native processor and a memory management unit. The processor is a micro-programmed, pipelined, Java-optimized processor (JOP), initially written in VHDL, and its BSV re-designed match BLUEJEP. Its memory management unit implements the bytecodes dealing with memory allocation, along with a mark-compact garbage collector. The two design flows are examined from several points of view, including both quantitative and qualitative measures. Based on this design experience, we conclude that the new high-abstraction level languages, such as BSV, offer in comparison to register-transfer (RT) level classic approaches roughly the same trade-offs that C++ offers vs. assembly language in the software world.