In-System FPGA Prototyping of an Itanium Microarchitecture

Authors:
Roland E. Wunderlich;James C. Hoe
Affiliations:
Computer Architecture Laboratory at Carnegie Mellon;Computer Architecture Laboratory at Carnegie Mellon
Venue:
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Year:
2004

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Abstract

We describe an effort to prototype an Itanium microarchitecture using an FPGA. The microarchitecture model is written in the Bluespec hardwaredescription language (HDL) and supports a subset of the Itanium instruction set architecture. The microarchitecture model includes details such as multi-bundle instruction fetch, decode and issue; parallel pipelined execution units with scoreboarding and predicated bypassing; and multiple levels of cache hierarchies. The microarchitecture model is synthesized and prototyped on a special FPGA card that allows the processor model to interface directly to the memory bus of a host PC. This is an effort toward developing a flexible microprocessor prototyping framework for rapid design exploration.