Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
Power Aware Interface Synthesis for Bus-Based SoC Designs
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A high performance bus communication architecture through bus splitting
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power analysis of system-level on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
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Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
PowerViP: Soc power estimation framework at transaction level
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Improving the scalability of SAMBA bus architecture
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint
Proceedings of the 43rd annual Design Automation Conference
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Broadcast filtering-aware task assignment techniques for low-power MPSoCs
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Broadcast filtering: Snoop energy reduction in shared bus-based low-power MPSoCs
Journal of Systems Architecture: the EUROMICRO Journal
SAMBA-bus: A high performance bus architecture for system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CAFES: A framework for intrachip application modeling and communication architecture design
Journal of Parallel and Distributed Computing
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This paper proposes split shared-bus architecture to reduce the energy dissipation for global data exchange among a set of interconnected modules. The bus splitting problem for minimum energy is formulated as a minimum-exchange bus split problem, which is shown to be NP-complete. The problem is solved heuristically by using a maximum-weight matching algorithm and combinatorial search. Experimental results show that the energy saving of split-bus architecture compared to monolithic-bus architecture varies from 16% to 50%, depending on the characteristics of the data transfer among the modules and the configuration of the split-bus. The proposed split-bus architecture can be extended to multiway split-bus architecture when large numbers of modules are to be connected