LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
Latency-guided on-chip bus network design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Architectural energy optimization by bus splitting
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improving the scalability of SAMBA bus architecture
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
SAMBA-bus: A high performance bus architecture for system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Topology synthesis of cascaded crossbar switches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pipelined bidirectional bus architecture for embedded multimedia socs
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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A high performance communication architecture, SAMBA-bus, isproposed in this paper. In SAMBA-bus, multiple compatible bustransactions can be performed simultaneously with only a singlebus access grant from the bus arbiter. Experimental results showthat, compared with a traditional bus architecture, the SAMBA-busarchitecture can have up to 3.5 times improvement in the effectivebandwidth, and up to 15 times reduction in the average communicationlatency. In addition, the performance of SAMBA-bus architectureis affected only slightly by arbitration latency, because bustransactions can be performed without waiting for the bus accessgrant from the arbiter. This feature is desirable in SoC designs withlarge numbers of modules and long communication delay betweenmodules and the bus arbiter.