Efficient co-simulation framework enhancing system-level power estimation for a platform-based SoC design

  • Authors:

  • Je-Hoon Lee;Sang-Choon Kim;Young Hwan Kim;Kyoungrok Cho

  • Affiliations:

  • Division of Electronic and Information Communication Engineering, Kangwon National University, Samcheok, Gangwon 245-711, Republic of Korea;Division of Electronic and Information Communication Engineering, Kangwon National University, Samcheok, Gangwon 245-711, Republic of Korea;Department of EE, Pohang University of Science and Technology, Pohang 790-784, Republic of Korea;WCU Program, College of Electrical and Computer Engineering, Chungbuk National University, Cheongju 361-763, Republic of Korea

  • Venue:
  • Microelectronics Journal
  • Year:
  • 2011

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Abstract

This paper proposes a hardware-software (HW-SW) co-simulation framework that provides a unified system-level power estimation platform for analyzing efficiently both the total power consumption of the target SoC and the power profiles of its individual components. The proposed approach employs the trace-based technique that reflects the real-time behavior of the target SoC by applying various operation scenarios to the high-level model of target SoC. The trace data together with corresponding look-up table (LUT) is utilized for the power analysis. The trace data is also used to reduce the number of input vectors required to analyze the power consumption of large H/W designs through the trade-offs between the signal probability in the trace results and its effect on the power consumption. The effect of cache miss on power, occurring in the S/W program execution, is also considered in the proposed framework. The performance of the proposed approach was evaluated through the case study using the SoC design example of IEEE 802.11a wireless LAN modem. The case study illustrated that, by providing fast and accurate power analysis results, the proposed approach can enable SoC designers to manage the power consumption effectively through the reconstruction of the target SoC. The proposed framework maps all hardware IPs into FPGA. The trace based approach gets input vectors at transactor of the each IP and gets power consumption indexing a LUT. This hardware oriented technique reports the power estimation result faster than the conventional ones doing it at S/W level.