Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
HAVEN: an open framework for FPGA-Accelerated functional verification of hardware
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Iterative routing algorithm of Inter-FPGA signals for Multi-FPGA prototyping platform
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
Towards beneficial hardware acceleration in HAVEN: evaluation of testbed architectures
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
Frequency optimization objective during system prototyping on multi-FPGA platform
International Journal of Reconfigurable Computing
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In modern SoC design flow, verification and validation are key components to reduce time-to-market and enhance product quality. To avoid trade-offs between timing accuracy and simulation speed in RTL simulation and C++/SystemC virtual prototyping, FPGA prototyping has become a better choice in the design flow. However, the time-consuming bring-up procedure and insufficient debugging visibility has impaired its potential strengths in verification and validation. In this paper, we present the technology from InPA Systems in which four different modes of operations, RTL-FPGA co-simulation, SystemC-FPGA co-emulation, vector prototyping, and in-circuit prototyping, are supported. With these different modes of FPGA operations, users can develop and verify their SoCs in different stages of the design flow with different abstraction levels. This methodology efficiently and robustly completes the SoC HW/SW verification and validation flow.