Re-use-centric architecture for a fully accelerated testbench environment
Proceedings of the 40th annual Design Automation Conference
Automatic translation of behavioral testbench for fully accelerated simulation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
SoC HW/SW verification and validation
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Reaching coverage closure in post-silicon validation
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
HAVEN: an open framework for FPGA-Accelerated functional verification of hardware
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
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Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. In our previous work, we developed HAVEN, an open verification framework that enables hardware acceleration of functional verification runs by moving the design under test (DUT) into a verification environment in a field-programmable gate array (FPGA). In the original version of HAVEN, the generator of input stimuli, the scoreboard and the transfer function still resided in a software simulator, and the peak acceleration ratio achieved was over 1,000. In the currently presented paper, we further extend HAVEN with hardware acceleration of the remaining parts of the verification environment. This enables the user to choose from several different testbed architectures which are evaluated and compared. We show that each architecture provides a different trade-off between the comfort of verification and the degree of acceleration. Using the highest degree of acceleration, we were able to achieve the speed-up in the order of hundreds of thousands while still being able to employ assertion and coverage analysis.