Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Postsilicon Validation Methodology for Microprocessors
IEEE Design & Test
Compacting regression-suites on-the-fly
APSEC '97 Proceedings of the Fourth Asia-Pacific Software Engineering and International Computer Science Conference
Probabilistic regression suites for functional verification
Proceedings of the 41st annual Design Automation Conference
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Shielding against design flaws with field repairable control logic
Proceedings of the 43rd annual Design Automation Conference
Advanced Analysis Techniques for Cross-Product Coverage
IEEE Transactions on Computers
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Automating post-silicon debugging and repair
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A probabilistic alternative to regression suites
Theoretical Computer Science
BackSpace: formal analysis for post-silicon debug
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Functional Verification Coverage Measurement and Analysis
Functional Verification Coverage Measurement and Analysis
EDA in IBM: past, present, and future
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 48th Design Automation Conference
Threadmill: a post-silicon exerciser for multi-threaded processors
Proceedings of the 48th Design Automation Conference
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
Leveraging accelerated simulation for floating-point regression
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
Towards beneficial hardware acceleration in HAVEN: evaluation of testbed architectures
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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Obtaining coverage information in post-silicon validation is a difficult task. Adding coverage monitors to the silicon is costly in terms of timing, power, and area, and thus even if feasible, is limited to a small number of coverage monitors. We propose a new method for reaching coverage closure in post-silicon validation. The method is based on executing the post-silicon exercisers on a pre-silicon acceleration platform, collecting coverage information from these runs, and harvesting important test templates based on their coverage. This method was used in the verification of IBM's POWER7 processor. It contributed to the overall high-quality verification of the processor, and specifically to the post-silicon validation and bring-up.