Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Postsilicon Validation Methodology for Microprocessors
IEEE Design & Test
Compacting regression-suites on-the-fly
APSEC '97 Proceedings of the Fourth Asia-Pacific Software Engineering and International Computer Science Conference
Industrial experience with test generation languages for processor verification
Proceedings of the 41st annual Design Automation Conference
Probabilistic regression suites for functional verification
Proceedings of the 41st annual Design Automation Conference
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Functional Verification Coverage Measurement and Analysis
Functional Verification Coverage Measurement and Analysis
POWER7: verification challenge of a multi-core processor
Proceedings of the 2009 International Conference on Computer-Aided Design
Reaching coverage closure in post-silicon validation
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
EDA in IBM: past, present, and future
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The growing importance of post-silicon validation in ensuring functional correctness of high-end designs has increased the need for synergy between the pre-silicon verification and post-silicon validation. This synergy starts with a common verification plan. It continues with common verification goals and shared tools and techniques. This paper describes our experience in improving this synergy in the pre- and post-silicon verification of IBM's POWER7 processor chip and by leveraging pre-silicon methodologies and techniques in the post-silicon validation of the chip.