The design and verification of the AlphaStation 600 5-series workstation
Digital Technical Journal - Special 10th anniversary issue
Digital Technical Journal - Special 10th anniversary issue
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
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ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Code generation and analysis for the functional verification of micro processors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Functional verification methodology for the PowerPC 604 microprocessor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Micro architecture coverage directed generation of test programs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Verification of the UltraSPARC microprocessor
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
Formal implementation verification of the bus interface unit for the Alpha 21264 microprocessor
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Post-silicon debugging for multi-core designs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Reaching coverage closure in post-silicon validation
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Proceedings of the 48th Design Automation Conference
Threadmill: a post-silicon exerciser for multi-threaded processors
Proceedings of the 48th Design Automation Conference
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Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Deconfigurable microprocessor architectures for silicon debug acceleration
Proceedings of the 40th Annual International Symposium on Computer Architecture
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ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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This paper presents a systematic methodology for microarchitecture focused postsilicon system validation in the context of IA-32 Intel microprocessors. The need for a rigorous microarchitecture focused postsilicon validation is first established after analyzing presilicon and postsilicon validation techniques that CPU manufacturers have primarily used. The proposed methodology targets microarchitectural attributes that are prioritized based on their criticality for validation to identify corner cases. Several test templates cover all the critical attributes. Each template has an algorithm covering a subset of the attributes and automatically generates many tests by parameterizing around the corner case. Examples of application of the methodology are presented. Tests based on prioritized attributes help in narrowing the search of the huge validation space for complex logic-interaction type bugs in the early phase of silicon validation. The important issues in design and deployment of such tests are described and our solutions are discussed.