Hardware/software co-simulation in a VHDL-based test bench approach
DAC '97 Proceedings of the 34th annual Design Automation Conference
A reconfigurable logic machine for fast event-driven simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
A transaction-based unified simulation/emulation architecture for functional verification
Proceedings of the 38th annual Design Automation Conference
A fast, inexpensive and scalable hardware acceleration technique for functional simulation
Proceedings of the 39th annual Design Automation Conference
Platform-Based Testbench Generation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Communication-efficient hardware acceleration for fast functional simulation
Proceedings of the 41st annual Design Automation Conference
A Layered Adaptive Verification Platform for Simulation, Test, and Emulation
IEEE Design & Test
Enhancing Performance of HW/SW Cosimulation and Coemulation by Reducing Communication Overhead
IEEE Transactions on Computers
Automatic translation of behavioral testbench for fully accelerated simulation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Emulating switch-level models of CMOS circuits
Microelectronic Engineering
Fast co-verification of HDL models
Microelectronic Engineering
Towards beneficial hardware acceleration in HAVEN: evaluation of testbed architectures
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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This paper presents a new technology that accelerates functional system verification. Starting with a behavioral testbench, we developed a seamless flow to generate a re-use-oriented architecture for a synthesizable testbench without loosing compatibility towith the original testbench. Consequently, we combine the flexibility of a behavioral testbench and the simulation performance of a synthesizable testbench, while greatly reducing the modeling overhead.The approach itself is hardware independent. To prove the usability of our approach, we verified a hard disc controller on an emulator. With this setup, we achieved a speed-up factor of 5000 versus plain simulation.