TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification

Authors:
Young-Il Kim;Chong-Min Kyung
Affiliations:
Korea Advanced Institute of Science and Technology;Korea Advanced Institute of Science and Technology Integrated Circuit Design Education Center
Venue:
IEEE Design & Test
Year:
2004

Citing 2
Cited 2

A reconfigurable logic machine for fast event-driven simulation

DAC '98 Proceedings of the 35th annual Design Automation Conference
Re-use-centric architecture for a fully accelerated testbench environment

Proceedings of the 40th annual Design Automation Conference

Enhancing Performance of HW/SW Cosimulation and Coemulation by Reducing Communication Overhead

IEEE Transactions on Computers
Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Editor's note: This hybrid dynamic simulation scheme implements part of the simulator in software running on a processor and maps the rest onto a programmable hardware accelerator. An algorithm for hardware synthesis of behavioral testbenches enables better partitions, resulting in lower communication costs between the two components. 驴Sharad Malik, Princeton University