Iterative routing algorithm of Inter-FPGA signals for Multi-FPGA prototyping platform

Authors:
Mariem Turki;Zied Marrakchi;Habib Mehrez;Mohamed Abid
Affiliations:
Laboratoire d'Informatique de Paris 6, Universite de Pierre et Marie Curie, Paris, France;Flexras Technologies, Paris, France;Laboratoire d'Informatique de Paris 6, Universite de Pierre et Marie Curie, Paris, France;CES Laboratory, Sfax University, Tunisia
Venue:
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
Year:
2013

Citing 8
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Abstract

Over the last few years, multi-FPGA-based prototyping becomes necessary to test System On Chip designs. However, the most important constraint of the prototyping platform is the interconnection resources limitation between FPGAs. When the number of inter-FPGA signals is greater than the number of physical connections available on the prototyping board, signals are time-multiplexed which decreases the system frequency. We propose in this paper an advanced method to route all the signals with an optimized multiplexing ratio. Signals are grouped then routed using the intra-FPGA routing algorithm: Pathfinder. This algorithm is adapted to deal with the inter-FPGA routing problem. Many scenarios are proposed to obtain the most optimized results in terms of prototyping system frequency. Using this technique, the system frequency is improved by an average of 12.8%.