Power optimization and management in embedded systems
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Software implementation strategies for power-conscious systems
Mobile Networks and Applications
Application-driven processor design exploration for power-performance trade-off analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Efficient Microprocessor Design Space Exploration through Statistical Simulation
ANSS '03 Proceedings of the 36th annual symposium on Simulation
Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies
Proceedings of the 31st annual international symposium on Computer architecture
Journal of Systems and Software - Special issue: Performance modeling and analysis of computer systems and networks
Improved automatic testcase synthesis for performance model validation
Proceedings of the 19th annual international conference on Supercomputing
Accurate memory data flow modeling in statistical simulation
Proceedings of the 20th annual international conference on Supercomputing
IEEE Transactions on Computers
Dispersing proprietary applications as benchmarks through code mutation
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Distilling the essence of proprietary workloads into miniature benchmarks
ACM Transactions on Architecture and Code Optimization (TACO)
Power efficient co-simulation framework for a wireless application using platform based SoC
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
SWEEP: evaluating computer system energy efficiency using synthetic workloads
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
| Hi-index | 0.04 |
This paper presents a new approach for estimating power dissipation in a high performance microprocessor chip. A characteristic profile (including parameters such as the cache miss rate, branch-prediction miss rate, pipeline stalls, instruction mix, and so on) is first extracted from the application programs. Mixed-integer linear-programming and heuristic rules are then used to gradually transform a generic program template into a fully functional program. The synthesized program exhibits the same characteristics (and hence the same performance and power-dissipation behavior), yet it has an instruction trace that is orders of magnitude smaller than the initial trace. The synthesized program is subsequently simulated on a register-transfer-level description of the target microprocessor to provide the power-dissipation value. Results obtained for Intel's Pentium processor executing standard benchmark programs show a simulation-time reduction of three to five orders of magnitude