Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Hardware/software co-simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Profile-driven program synthesis for evaluation of system power dissipation
DAC '97 Proceedings of the 34th annual Design Automation Conference
System-level synthesis of low-power hard real-time systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
COSYN: hardware-software co-synthesis of embedded systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
Fast power estimation for deterministic input streams
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Software timing analysis using HW/SW cosimulation and instruction set simulator
Proceedings of the 6th international workshop on Hardware/software codesign
A case study on modeling shared memory access effects during performance analysis of HW/SW systems
Proceedings of the 6th international workshop on Hardware/software codesign
Power estimation of embedded systems: a hardware/software codesign approach
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low power hardware/software partitioning approach for core-based embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Cycle-accurate simulation of energy consumption in embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Energy-efficient design of battery-powered embedded systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits
Dynamic Power Management: Design Techniques and CAD Tools
Dynamic Power Management: Design Techniques and CAD Tools
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Low Power Digital CMOS Design
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Sequence compaction for power estimation: theory and practice
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SEAS: a system for early analysis of SoCs
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Cycle-accurate power analysis for multiprocessor systems-on-a-chip
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors
IEEE Transactions on Computers
Petri nets tools integration through Eclipse
eclipse '05 Proceedings of the 2005 OOPSLA workshop on Eclipse technology eXchange
PowerViP: Soc power estimation framework at transaction level
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Power macromodeling of MPSoC message passing primitives
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Accelerating system-on-chip power analysis using hybrid power estimation
Proceedings of the 44th annual Design Automation Conference
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS)
System-level PVT variation-aware power exploration of on-chip communication architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power efficient co-simulation framework for a wireless application using platform based SoC
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
An emulation-based real-time power profiling unit for embedded software
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
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We present efficient power estimation techniques for hardware-software (HW-SW) system-on-chip (SoC) designs. Our techniques are based on concurrent and synchronized execution of multiple power estimators that analyze different parts of the SoC (we refer to this as coestimation), driven by a system-level simulation master. We motivate the need for power coestimation, and demonstrate that performing independent power estimation for the various system components can lead to significant errors in the power estimates, especially for control-intensive and reactive-embedded systems.We observe that the computation time for performing power coestimation is dominated by: i) the requirement to analyze/ simulate some parts of the system at lower levels of abstraction in order to obtain accurate estimates of timing and switching activity information and ii) the need to communicate between and synchronize the various simulators. Thus, a naive implementation of power coestimation may be too inefficient to be used in an iterative design exploration framework. To address this issue, we present several acceleration (speed-up) techniques for power coestimation. The acceleration techniques are energy caching, software power macro-modeling, and statistical sampling. Our speed-up techniques reduce the workload of the power estimators for the individual SoC components, as well as their communication/synchronization overhead. Experimental results indicate that the use of the proposed acceleration techniques results in significant (8 × to 87 ×) speed-ups in SOC power estimation time, with minimal impact on accuracy. We also show the utility of our coestimation tool to explore system-level power tradeoffs for a TCP/IP check-sum engine subsystem.