Experience with image compression chip design using unified system construction tools
DAC '94 Proceedings of the 31st annual Design Automation Conference
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Cycle-accurate simulation of energy consumption in embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Cost based tradeoff analysis of standard cell designs
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
GTX: the MARCO GSRC technology extrapolation system
Proceedings of the 37th Annual Design Automation Conference
Efficient power co-estimation techniques for system-on-chip design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On rent's rule for rectangular regions
Proceedings of the 2001 international workshop on System-level interconnect prediction
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Low Power Digital CMOS Design
Battery-Driven System Design: A New Frontier in Low Power Design
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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We present a novel technique to predict energy and power consumption in an electronic system, given its behavioral specification and library components. The early prediction gives circuit designers the freedom to make numerous high-level choices (such as die size, package type, and latency of the pipeline) with confidence that the final implementation will meet power and energy as well as cost and performance constraints. Our unique statistical estimation technique associates low-level, technology dependent physical and electrical parameters, with expected circuit resources and interconnect. Further correlations with switching activity yield accurate results consistent with implementations. All feasible designs are investigated using this technique and the designer may tradeoff between small size, high speed, low energy, and low power. The results for designs of two popular signal processing applications, predicted prior to synthesis, are within 10% accuracy of power estimates performed on synthesized layouts.