Interconnect characteristics of 2.5-D system integration scheme
Proceedings of the 2001 international symposium on Physical design
Circuit-simulated obstacle-aware Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures
Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures
Obstacle-aware longest path using rectangular pattern detouring in routing grids
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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Progressive scaling of technology node has serious impacts on the performance of VLSI circuits. A major influencing factor is the dominance of interconnect delay, and its associated effects such as excessive power consumption, signal integrity issues, and so on. 3D architectures were proposed as an alternative to the classical 2D architectures with certain specific advantages such as reduced interconnect lengths, and hence the delay. However, negative issues like through-silicon vias (TSVs), excessive heating effects etc also come into play. Routing problem in 3D ICs becomes even more complicated in presence of obstacles across the routing layers. In this paper, in an attempt to gain a better insight of the use of interconnects in 3D architectures,we propose a method for routing of nets in the 3D architecture with the presence of obstacles across the routing layers, and perform empirical study in terms of total interconnection lengths across the layers as well as the inter-layer cost involved in TSV.