Hierarchical analysis of power distribution networks
Proceedings of the 37th Annual Design Automation Conference
Interconnect characteristics of 2.5-D system integration scheme
Proceedings of the 2001 international symposium on Physical design
Computer Methods for Circuit Analysis and Design
Computer Methods for Circuit Analysis and Design
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
Design and Analysis of Power Distribution Networks with Accurate RLC Models
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compact thermal modeling for temperature-aware design
Proceedings of the 41st annual Design Automation Conference
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Timing
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient full-chip thermal modeling and analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Floorplanning for 3-D VLSI design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Integrating dynamic thermal via planning with 3D floorplanning algorithm
Proceedings of the 2006 international symposium on Physical design
A routing algorithm for flip-chip design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
3D floorplanning with thermal vias
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design for Manufacturability and Yield for Nano-Scale CMOS
Design for Manufacturability and Yield for Nano-Scale CMOS
Interconnects in the third dimension: design challenges for 3D ICs
Proceedings of the 44th annual Design Automation Conference
An integer linear programming based routing algorithm for flip-chip design
Proceedings of the 44th annual Design Automation Conference
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
Thermal-Aware 3D IC Placement Via Transformation
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical placer for mixed-size 3D placement
Proceedings of the 19th international symposium on Physical design
TSV stress aware timing analysis with applications to 3D-IC layout optimization
Proceedings of the 47th Design Automation Conference
ILP-based inter-die routing for 3D ICs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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Today's SoCs/SIPs face numerous design challenges as increased integration of system components on a single die stretches the limits of technology and design capacity. 3D integration, where multiple dies are stacked and interconnected in the vertical dimension using through-silicon vias (TSVs), is probably the best hope for carrying ICs along (and even beyond) the path of Moore's law in the 21st century. However successful adoption of 3D ICs will require among other things modifications to EDA tools to enable 3D IC design. In this paper, we identify key stages in EDA that need modification to handle 3D ICs, highlight the challenges and review existing solutions, if they exist. Whenever appropriate, at a particular stage, we also provide preferred features of the solutions necessary to enable 3D IC design with the least amount of disruption.