Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
Thermal-Aware 3D IC Placement Via Transformation
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Foundations and Trends in Electronic Design Automation
Thermal aware placement in 3D ICs using quadratic uniformity modeling approach
Integration, the VLSI Journal
Modern Circuit Placement: Best Practices and Results
Modern Circuit Placement: Best Practices and Results
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs
Proceedings of the 2009 International Conference on Computer-Aided Design
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Proceedings of the 2009 International Conference on Computer-Aided Design
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Robust Mixed-Size Legalization and Detailed Placement Algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Highly Efficient Gradient Computation for Density-Constrained Analytical Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting die-to-die thermal coupling in 3D IC placement
Proceedings of the 49th Annual Design Automation Conference
Multiobjective optimization of deadspace, a critical resource for 3D-IC integration
Proceedings of the International Conference on Computer-Aided Design
Thermomechanical stress-aware management for 3D IC designs
Proceedings of the Conference on Design, Automation and Test in Europe
Compact lateral thermal resistance modeling and characterization for TSV and TSV array
Proceedings of the International Conference on Computer-Aided Design
From design to design automation
Proceedings of the 2014 on International symposium on physical design
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Existing thermal-aware 3D placement methods assume that the temperature of 3D ICs can be optimized by properly distributing the power dissipations, and ignoring the heat conductivity of though-silicon-vias (TSVs). However, our study indicates that this is not exactly correct. While considering the thermal effect of TSVs during placement appears to be quite complicated, we are able to prove that when the TSV area in each bin is proportional to the lumped power consumption in that bin, together with the bins in all the tiers directly above it, the peak temperature is minimized. Based on this criterion, we implement a thermal-aware 3D placement tool. Compared to the methods that prefer a uniform power distribution that only results in an 8% peak temperature reduction, our method reduces the peak temperature by 34% on average with even slightly less wirelength overhead. These results suggest that considering thermal effects of TSVs is necessary and effective during the placement stage. To the best of the authors' knowledge, this is the first thermal-aware 3D placement tool that directly takes into consideration the thermal and area impact of TSVs.