A multilevel analytical placement for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
An analytical placer for mixed-size 3D placement
Proceedings of the 19th international symposium on Physical design
Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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3D ICs has the potential to reduce the interconnect delay, but thermal problem becomes one of the most serious challenges. In this paper, we proposed an efficient thermal aware 3D placement algorithm based on an efficient 3D DCT placement which unified cell distribution and wire length into one quadratic function through cosine transformation (DCT) and utilized iterative quadratic placement idea to get the solution. To utilize the advantage of DCT idea, thermal dissipation, cell distribution and wire length are integrated together elegantly in our proposed thermal aware placement algorithm. Thermal distribution was considered enough during placement process even when a cell was moved. Two fast methods to reflect thermal charge were proposed for thermal distribution computation. The experimental results shows our thermal aware 3D placement algorithm is efficient with about 3% reduction in average temperature and 15% in max temperature but a little perturbation on wirelength.