A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits
Proceedings of the 41st annual Design Automation Conference
Analog layout generator for CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analog placement based on symmetry-island formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DeFer: deferred decision making enabled fixed-outline floorplanning algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A power optimization method for CMOS op-amps using sub-space based geometric programming
Proceedings of the Conference on Design, Automation and Test in Europe
An automated design tool for analog layouts
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Routability-driven analytical placement for mixed-size circuit designs
Proceedings of the International Conference on Computer-Aided Design
Heterogeneous B*-trees for analog placement with symmetry and regularity considerations
Proceedings of the International Conference on Computer-Aided Design
Fast analog layout prototyping for nanometer design migration
Proceedings of the International Conference on Computer-Aided Design
Practical placement and routing techniques for analog circuit designs
Proceedings of the International Conference on Computer-Aided Design
Routability-driven placement algorithm for analog integrated circuits
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Non-uniform multilevel analog routing with matching constraints
Proceedings of the 49th Annual Design Automation Conference
BLADES: an artificial intelligence approach to analog circuit design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal design of a CMOS op-amp via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Integrated Layout-Synthesis Approach for Analog ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Constraint-Based Layout-Driven Sizing of Analog Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In modern technology, layout effects have more and more impacts on circuit performance. However, most of the existing analog automation tools consider the circuit sizing and layout generation in two separate steps, which often result in time-consuming sizing-layout iterations. In this paper, a layout-aware analog synthesis tool is presented to generate the required designs from specifications to layout through a user-friendly GUI. In order to provide a strong link between sizing and layout steps, a parasitic-aware circuit sizing flow is proposed based on a flexible layout template to prevent the performance from failing to meet the specifications after layout. Routability-aware analog placement is then performed with a simple routing algorithm to generate the corresponding layout with minimized cost. As demonstrated in the experimental results, this analog synthesis tool is able to generate the required circuits in seconds with high quality layouts and effectively guarantees the post-layout performance with less over-design.