Design of pipeline analog-to-digital converters via geometric programming
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Automated design of operational transconductance amplifiers using reversed geometric programming
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Simulation-based reusable posynomial models for MOS transistor parameters
Proceedings of the conference on Design, automation and test in Europe
Evaluation of fully-integrated switching regulators for CMOS process technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CMOS op-amp power optimization in all regions of inversion using geometric programming
Proceedings of the 21st annual symposium on Integrated circuits and system design
Optimal design of a CMOS op-amp via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMOS op-amp sizing using a geometric programming formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LASER: layout-aware analog synthesis environment on laker
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Proceedings of the Conference on Design, Automation and Test in Europe
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A new sub-space max-monomial modeling scheme for CMOS transistors in sub-micron technologies is proposed to improve the modeling accuracy. Major electrical parameters of CMOS transistors in each sub-space from the design space are modeled with max-monomials. This approach is demonstrated to have a better accuracy for sub-micron technologies than single-space models. Sub-space modeling based geometric programming power optimization has been successfully applied to three different op-amps in 0.18μm technology. HSPICE simulation results show that sub-space modeling based GP optimization can allow efficient and accurate analog design. Computational effort can be managed to an acceptable level when searching sub-spaces for transistors by using practical constraints. An efficient scheme in dealing with non-convex constraint inherent in Kirchhoff's voltage law is suggested in this paper. By using this scheme, the non-convex constraint, such as posynomial equality, can be relaxed to a convex constraint without affecting the result.