ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Incremental logic synthesis through gate logic structure identification
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Incremental Synthesis for Engineering Changes
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Design and design automation of rectification logic for engineering change
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Logic synthesis for engineering change
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
AutoFix: a hybrid tool for automatic logic rectification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A metal-only-ECO solver for input-slew and output-loading violations
Proceedings of the 2009 international symposium on Physical design
New spare cell design for IR drop minimization in Engineering Change Order
Proceedings of the 46th Annual Design Automation Conference
Matching-based minimum-cost spare cell selection for design changes
Proceedings of the 46th Annual Design Automation Conference
Spare cells with constant insertion for engineering change
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A metal-only-ECO solver for input-slew and output-loading violations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ECO timing optimization using spare cells and technology remapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
X-architecture obstacles-avoiding routing with ECO consideration
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
ECO-aware obstacle-avoiding routing tree algorithm
WSEAS Transactions on Circuits and Systems
Reconfigurable ECO cells for timing closure and IR drop minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Match and replace: a functional ECO engine for multi-error circuit rectification
Proceedings of the International Conference on Computer-Aided Design
Timing ECO optimization via Bézier curve smoothing and fixability identification
Proceedings of the International Conference on Computer-Aided Design
Timing ECO optimization using metal-configurable gate-array spare cells
Proceedings of the 49th Annual Design Automation Conference
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In the VLSI design process, a design implementation often needs to be corrected because of new specifications or design constraint violations. This correction process is referred to as engineering change (EC). Usually, an EC problem is resolved by using spare cells, which have been inserted into the unused spaces of a chip. In this paper, we propose an iterative method to generate feasible mapping solutions for an EC problem considering spare cells whose inputs may be tied to Vdd or Gnd, called constant insertion. Applying constant insertion can increase a cell's flexibility in aspect of functionalities, so far-away spare cells need not be used just for some specific functionality. Our experimental results show that the area in which there are enough spare cells for a mapping solution with constant insertion is only 82% of the area without constant insertion.