Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A timing-constrained algorithm for simultaneous global routing of multiple nets
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
A Novel Performance-Driven Topology Design Algorithm
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Automating post-silicon debugging and repair
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
ECO timing optimization using spare cells
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Engineering change using spare cells with constant insertion
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Reap what you sow: spare cells for post-silicon metal fix
Proceedings of the 2008 international symposium on Physical design
A metal-only-ECO solver for input-slew and output-loading violations
Proceedings of the 2009 international symposium on Physical design
An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In the paper, we formulate a novel obstacle-avoiding engineering change ordering (ECO) driven minimal tree construction problem. The objective is to build a better routing tree in the sense of increasing ECO flexibility to force the routing tree pass through regions in which more spare cells are available so that the additional total wirelength compared to a conventional wirelength oriented routing tree can be minimized. We incorporate the concept of inserting the virtual nodes which indicate sub-regions having more available spare cells by evaluating the distribution of spare cells. With the terminals, the corners of obstacles and the added virtual nodes, a routing tree is then constructed. Experimental results show that the number of available spare cells near the routing tree constructed by our algorithm is increased up to 65.82%, while only 2.08% of additional total wirelength.