Introduction to algorithms
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Incremental logic synthesis through gate logic structure identification
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Incremental Synthesis for Engineering Changes
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Design and design automation of rectification logic for engineering change
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ECO timing optimization using spare cells
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Engineering change using spare cells with constant insertion
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Logic synthesis for engineering change
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
AutoFix: a hybrid tool for automatic logic rectification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ECO timing optimization using spare cells and technology remapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TRECO: dynamic technology remapping for timing engineering change orders
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Simultaneous functional and timing ECO
Proceedings of the 48th Design Automation Conference
Redundant-wires-aware ECO timing and mask cost optimization
Proceedings of the International Conference on Computer-Aided Design
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Engineering change (EC) is the process of modifying a VLSI design implementation to eliminate design errors, to add new specifications, or to correct design constraint violations. Usually, an EC problem is resolved by using spare cells that have been inserted into unused spaces on a chip. In this paper, we describe an iterative method to determine feasible mapping solutions for an EC problem considering spare cells whose inputs can be connected to Vdd or Gnd. Setting some of the cell inputs to fixed values is referred to as constant insertion. Constant insertion can increase cells' functional flexibility. Our experimental results suggest that constant insertion reduces the area required to find a feasible mapping solution to 80% of that with no constant insertion for the selected EC equations. We also show a procedure for modifying the initial feasible EC solution such that the routing or timing improves.