Synthesis by delayed binding of decisions
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Establishment of higher level logic design for very large scale computer
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A high level synthesis tool for MOS chip design
DAC '84 Proceedings of the 21st Design Automation Conference
Polaris: Polarity propagation algorithm for combinational logic synthesis
DAC '84 Proceedings of the 21st Design Automation Conference
LSS: a system for production logic synthesis
IBM Journal of Research and Development
An overview of logic synthesis systems
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Basic concepts of timing-oriented design automation for high-performance mainframe computers
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DAC '94 Proceedings of the 31st annual Design Automation Conference
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Principles of design automatioon system for very large scale computer design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Establishment of higher level logic design for very large scale computer
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Behavioral synthesis via engineering change
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Engineering change using spare cells with constant insertion
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Spare cells with constant insertion for engineering change
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DeltaSyn: an efficient logic difference optimizer for ECO synthesis
Proceedings of the 2009 International Conference on Computer-Aided Design
Line-level incremental resynthesis techniques for FPGAs
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper describes incremental logic synthesis for supporting function logic changes in the physical design stage of digital systems. The incremental logic synthesis is distinguished from logic synthesis in the respect that it updates only gate logic components, which must be changed due to the function logic changes, in the physically optimized gate logic structure. For making the incremental logic synthesis feasible, a gate logic structure identification and editing system has been developed with a corresponding gate matrix method as its core. This system has greatly contributed to the increase in design efficiency of the very large computer series M68XH.