ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Incremental logic synthesis through gate logic structure identification
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
ISPD '00 Proceedings of the 2000 international symposium on Physical design
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Implicit enumeration of structural changes in circuit optimization
Proceedings of the 41st annual Design Automation Conference
SAT sweeping with local observability don't-cares
Proceedings of the 43rd annual Design Automation Conference
The coming of age of physical synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Timing optimization by restructuring long combinatorial paths
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Improved Design Debugging Using Maximum Satisfiability
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Towards automated ECOs in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Incremental Verification with Error Detection, Diagnosis, and Visualization
IEEE Design & Test
Logic synthesis for engineering change
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An ECO routing algorithm for eliminating coupling-capacitance violations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ECO-System: Embracing the Change in Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BooM: a decision procedure for boolean matching with abstraction and dynamic learning
Proceedings of the 47th Design Automation Conference
Proceedings of the Conference on Design, Automation and Test in Europe
Line-level incremental resynthesis techniques for FPGAs
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Design methodology for the IBM POWER7 microprocessor
IBM Journal of Research and Development
Simultaneous functional and timing ECO
Proceedings of the 48th Design Automation Conference
Interpolation-based incremental ECO synthesis for multi-error logic rectification
Proceedings of the 48th Design Automation Conference
Match and replace: a functional ECO engine for multi-error circuit rectification
Proceedings of the International Conference on Computer-Aided Design
Boolean matching of function vectors with strengthened learning
Proceedings of the International Conference on Computer-Aided Design
A robust functional ECO engine by SAT proof minimization and interpolation techniques
Proceedings of the International Conference on Computer-Aided Design
Intuitive ECO synthesis for high performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Partial synthesis through sampling with and without specification
Proceedings of the International Conference on Computer-Aided Design
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During the IC design process, functional specifications are often modified late in the design cycle, after placement and routing are completed. However, designers are left either to manually process such modifications by hand or to restart the design process from scratch---a very costly option. In order to address this issue, we present DeltaSyn, a method for generating a highly optimized logic difference between a modified high-level specification and an implemented design. DeltaSyn has the ability to locate boundaries in implemented logic within which changes can be confined. DeltaSyn demarcates the boundary in two phases. The first phase employs fast functional and structural analysis techniques to identify equivalent signals forming the input-side boundary of the changes. The second phase locates the outputside boundary of the changes through a novel dynamic algorithm that detects matching logic downstream from the changes required by the ECO. Experiments on industrial designs show that together these techniques successfully implement ECOs while preserving an average of 97% of the existing logic. Unlike previous approaches, the use of bitparallel logic simulation and fast SAT solvers enables high performance and scalability. DeltaSyn can process and verify a typical ECO for a design of around 10K gates in about 200 seconds or less.