Rectification method for lookup-table type FPGA's
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Error correction based on verification techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Design and design automation of rectification logic for engineering change
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
SAT sweeping with local observability don't-cares
Proceedings of the 43rd annual Design Automation Conference
Automating Logic Rectification by Approximate SPFDs
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Towards automated ECOs in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
DeltaSyn: an efficient logic difference optimizer for ECO synthesis
Proceedings of the 2009 International Conference on Computer-Aided Design
A robust functional ECO engine by SAT proof minimization and interpolation techniques
Proceedings of the International Conference on Computer-Aided Design
Logic synthesis for engineering change
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
AutoFix: a hybrid tool for automatic logic rectification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design error diagnosis and correction via test vector simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fixing Design Errors With Counterexamples and Resynthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Intuitive ECO synthesis for high performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
A counterexample-guided interpolant generation algorithm for SAT-based model checking
Proceedings of the 50th Annual Design Automation Conference
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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To cope with last-minute design bugs and specification changes, engineering change order (ECO) is usually performed toward the end of the design process. This paper proposes an automatic ECO synthesis algorithm by interpolation. In particular, we tackle the problem by a series of partial rectifications. At each step, partial rectification can reduce the functional difference between an old implementation and a new specification. Our algorithm is especially effective for multiple error circuits. Experimental results show the proposed method is far superior to the most recent work and scales well on a set of large circuits.